林英超

Accepted Papers to be Published

1. Wei Cheng, Ing-Chao Lin and Yun-Yang Shih, "An Efficient Implementation of Convolutional Neural Network With CLIP-Q Quantization on FPGA," To appear in IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, doi: 10.1109/TCSI.2022.3193031.
2. Fang-Yi Gu, Ing-Chao Lin, and Jia-Wei Lin, "A Low-Power and High-Accuracy Approximate Multiplier With Reconfigurable Truncation," in IEEE Access, vol. 10, pp. 60447-60458, 2022
3. Jilan Lin, Cheng-Da Wen, Xing Hu, Tianqi Tang, Ing-Chao Lin, Yu Wang, and Yuan Xie "Rescuing RRAM-based Computing from Static and Dynamic Faults" IEEE Transactions on Computer-Aided Design on Integrated Circuits
4. Ing-Chao Lin, Chi-Huan Tang, Chi-Ting Ni, Xing Hu, Yu-Tong Shen, Pei-Yin Chen, and Yuan Xie "A Novel, Efficient Implementation of a Local Binary Convolutional Neural Network" IEEE Transactions on Circuit and Systems II

Refered Papers

1. Wei Cheng, Ing-Chao Lin and Yun-Yang Shih, "An Efficient Implementation of Convolutional Neural Network With CLIP-Q Quantization on FPGA," To appear in IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, doi: 10.1109/TCSI.2022.3193031.
   
2. Fang-Yi Gu, Ing-Chao Lin, and Jia-Wei Lin, "A Low-Power and High-Accuracy Approximate Multiplier With Reconfigurable Truncation," in IEEE Access, vol. 10, pp. 60447-60458, 2022
3. Ing-Chao Lin, Da-Wei Chang, Wei-Jun Chen, Jian-Ting Ke, and Po-Han Huang "Global Clean Page First Replacement and Index Aware Multi-Stream Prefetcher in Hybrid Memory Architecture" IEEE Transactions on Computer-Aided Design on Integrated Circuits, vol. 39, no.9, pp. 1750-1763, Sept. 2020(SCI, EI)
4. Ing-Chao Lin, Wei-Ting Chen, Yu-Cheng Chou, and Pei-Yin Chen "A Novel Comparison-Free 1D Median Filter" IEEE Transactions on Circuit and Systems II, vol. 67, no. 7, pp. 1329-1333, July 2020(SCI, EI)
5. Jing-Yuan Luo, Hsiang-Yun Cheng, Ing-Chao Lin, Da-Wei Chang, and Chien-Lun Lo "TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration" IEEE Transactions on Computers (TC), vol. 68, no. 12, pp. 1704-1719, 2019(SCI, EI)
6. Ing-Chao Lin, Da-Wei Chang, Chen-Tai Kao, and Sheng-Xuan Lin "Infection-Based Dead Page Prediction in Hybrid Memory Architecture" IEEE Transactions on VLSI (TVLSI) System, vol. 27, no. 10, pp. 2401-2412, 2019(SCI, EI)
7. Da-Wei Chang, Ing-Chao Lin, Yi-Chiao Lin, and Wen-Zhi Huang "OCMAS: Online Page Clustering for Multi-Bank Scratchpad Memory" IEEE Trans on Computer-Aided Design on Integrated Circuits (TCAD), vol. 38, no. 2, pp. 220-233(SCI, EI)
8. Ing-Chao Lin, Yun Kae Law, Yuan Xie "Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes" Transaction on VLSI Systems (TVLSI) , vol. 26, no. 1, pp. 50-62. 2018 (SCI, EI)
9. Da-Wei Chang, Ing-Chao Lin*, and Lin-Chun Yong "ROHOM: Requirement-aware Online Hybrid On-chip Memory Management for Multicore Systems" IEEE Trans on Computer-Aided Design on Integrated Circuits, vol. 36, no. 3, pp. 357 - 369, 2017 (SCI, EI)
10. Ing-Chao Lin, Yen-Han Lee, and Sheng-Wei Wang "Reducing Aging Effect on Ternary CAM" IEICE Transactions on Electronics Vol.E99-C No.7 pp.878-891, 2016 (SCI, EI)
11. Ing-Chao Lin* and Jeng-Nian Chiou "High-Endurance Hybrid Cache Design in CMP Architecture with Cache Partitioning and Access-Aware Policies" IEEE Trans. on Very Large Scale Integration Systems (TVLSI), vol. 23, no. 10, pp. 2149-2161, 2015 (SCI EI)
12. Ing-Chao Lin, Yi-Ming Yang, and Cheng-Chien Lin "High-Performance Low-Power Carry Speculative Addition with Variable Latency" IEEE Trans. on Very Large Scale Integration Systems (TVLSI), vol. 23, no. 9, pp. 1591-1603, 2015 (SCI EI)
13. Ing-Chao Lin*, Yu-Hung Cho, and Yi-Ming Yang "Aging-Aware Reliable Multiplier With Adaptive Hold Logic" IEEE Trans. on VLSI (TVLSI) Systems vol. 23, no. 3, pp. 544-556, March 2015 (SCI EI)
14. Da-Wei Chang, Ing-Chao Lin*, Yu-Shiang Chien, Ching-Lun Lin, Alvin W. Y. Su, and Chung-Ping Young "CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management" IEEE Trans. on Computer-Aided Design on Integrated Circuits (TCAD), vol. 33, pp. 1806-1817, Dec. 2014 (SCI EI)
15. Kai-Chiang Wu, Ing-Chao Lin, and Yao-Te Wang "BTI-aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs" IEEE Trans. on Computer-Aided Design on Integrated Circuits (TCAD), vol. 33, no. 10, pp.1591-1595, Oct. 2014 (SCI EI)
16. Ing-Chao Lin*, Shun-Ming Syu, and Tsung-Yi Ho "NBTI Tolerance and Leakage Reduction using Gate Sizing" ACM Journal on Emerging Technologies in Computing Systems (JETC) , vol. 11, no. 1, pp. 1-12, Sep. 2014 (SCI EI)
17. Ing-Chao Lin*, Kuan-Hui Li, Chia-Hao Lin, and Kai-Chiang Wu "NBTI and Leakage Reduction Using ILP-based Approach" IEEE Trans. on Very Large Scale Integration Systems (TVLSI) , vol. 22, no. 9, pp. 2034-2038, Sep. 2014 (SCI EI)
18. Yi-Hua Li, Wei-Cheng Lien, Ing-Chao Lin, and Kuen-Jong Lee "Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing" IEEE Trans. on Computer-Aided Design on Integrated Circuits (TCAD), vol. 33, no. 1, pp. 127-138, Jan. 2014 (SCI EI)
19. N. Dhanwada, R. Bergamaschi2, W. Dungan, I. Nair, P. Gramann, W. Dougherty and I.-C. Lin "Transaction-Level Modeling for Architectural and Power Analysis of PowerPC and CoreConnect based Systems" Journal of Design Automation for Embedded Systems (SCI EI)
20. Ing-Chao Lin*, Chin-Hong Lin, and Kuan-Hui Li "Leakage and Aging Optimization Using Transmission Gate-Based Technique" IEEE Trans. on Computer-Aided Design on Integrated Circuits, vol. 32, no. 1, pp. 87-99, Jan. 2013 (SCI EI)

Conference Papers

國際會議

1. 1. Yan-Han Lee, Ing-Chao Lin, and Shen-Wei Wang "Impact of NBTI and PBTI effects on Ternary CAM" To appear in ISQED 2013 (EI)
2. 2. Shun-Ming Syu, Yu-Hui Shao, and Ing-Chao Lin "High-Endurance Hybrid Cache Design in CMP Architecture with Cache Partitioning and Access-Aware Policy" To appearing in GLSVLSI 2013 (EI)
3. 3. Yu-Hung Cho, Ing-Chao Lin, and Yi-Ming Yang "Aging-aware Reliable Multiplier Design" Proceedings of IEEE International Conference on SoC Conference (SoCC) 2012EI
4. 4. Yao-Te Wang and Ing-Chao Lin "Analyzing BTI effects on retention registers" Proceedings of Asia Symposium of Quality Electronic Design (ASQED) 2012EI
5. 5. S.-Q. Zheng, I.-C. Lin, and Y.-H. Lee "Analyzing throughput of power and thermal-constraint multicore processor under NBTI effect" Proceedings of Great Lakes Symposium on VLSI (GLSVLSI) 2011EI
6. 6. C.-H. Lin, I.-C. Lin, and K.-H. Li "TG-based technique for NBTI degradation and leakage optimization" Proceedings of International Symposium on Low Power Electronics and Design (ISLPED) 2011EI
7. 7. S.-Q. Zheng and I.-C. Lin "Transaction-level error susceptibility for bus-based System-on-Chip: From single-bit to multi-bit" Proc. of International Computer Symposium (ICS) 2010EI
8. 8. I.-C. Lin and V. Narayanan "System Level Power and Reliability Modeling" Design, Automation and Test in Europe Conference and Exhibition 2007
9. 9. I.-C. Lin, S. Srinivasan, V. Narayanan, N. Dhanwada "Transaction Level Error Susceptibility Model for Bus Based SoC Architectures" Proceeding of International Symposium on Quality Electronic Design 2006
10. 10. I.-C. Lin and V. Narayanan "Transaction Level Power Modeling for PCI Express" TECHCON 2005
11. 11. N. Dhanwada, I.-C. Lin and V. Narayanan "A Power Estimation Methodology for SystemC Transaction Level Models" Proceeding of International Conference on Hardware/Software Codesign and System Synthesis 2005
12. 12. N. Dhanwada, R. Bergamaschi, W. Dungan, I. Nair, W. Dougherty, Y. Shin, S. Bhattacharya, I. Lin, J. Darringer, S. Paliwa "Simultaneous Exploration of Power, Physical Design and Architectural Performance Dimensions of the SoC Design Space using SEAS" IP Based SoC Design Forum & Exhibition 2004

國內會議

1. 1. Yu-Hung Cho, Ing-Chao Lin, and Yi-Ming Yang "Aging-aware Reliable Multiplier Design" Proceeding of VLSI/CAD Symposium 2012
2. 2. Kuan-Hui Li, Ing-Chao Lin Li, and Jia-Hao Lin "NBTI Mitigation and Leakage Reduction Using ILP" Proceedings of VLSI/CAD Symposium 2012
3. 3. K.-H. Li, C.-H. Lin, and I.-C. Lin "TG-based Technique for NBTI Degradation and Leakage Optimization" Proceedings of VLSI/CAD Symposium 2011
4. 4. S.-Q. Zheng, I.-C. Lin "Mitigating NBTI using Core Rotation and Scheduled Voltage Scaling" Proc. of VLSI/CAD Symposium 2011

科技部計劃

一般建教案

指導學生

博士班:

顧芳宜(博110)、楊琳淳(博104)

碩士班:

劉品宏(碩110)、伍志忠(碩110)、鄒柏宇(碩110)、陳韋綸(碩110)、鄭維(碩109)
楊承翰(碩109)、王傑世(碩109)、謝宜紘(碩109)、陳柏廷(碩109)、林家葦(碩108)
曾士峰(碩108)、黃俞紘(碩108)、溫承達(碩107)、陳昱霖(碩107)、阮德日光(碩107)
林聖軒(碩106)、沈育同(碩106)、施鈞陽(碩106)、羅健倫(碩105)、柯建廷(碩105)
高鎮泰(碩104)、陳緯峻(碩104)、周宇承 (碩104)、羅靖淵(碩104)、張鶴騰(碩103)
邱坤瑋(碩103)、劉運凱(碩102)、王正綱(碩102)、林承謙(碩102)、楊順翔(碩102)
邵玉輝(碩101)、粘光裕(碩101)、裘証年(碩101)、王耀德(碩100)、楊顗民(碩100)
許順明(碩100)、王聖瑋(碩100)、林家豪(碩100)、卓育弘(碩99)、李怡樺(碩99)
李彥翰(碩99)、李冠輝(碩99)、鄭世群(碩98)、林晉弘(碩98)

指導學生之特殊榮譽

• 2019 中華民國資訊學會最佳碩博士論文獎 (學生柯建廷)
• 2015 Taiwan IEEE Best Ph.D. Thesis Award - Honorable mention
• 2015 全國大學校院智慧電子系統設計競賽 核心技術組 優等
• 2014國際積體電路電腦輔助設計體製作競賽 優等 (陳境圃)
• 2014國際積體電路電腦輔助設計體製作競賽 特優
• 2014 IEEE Tainan Section Best Master Thesis Award
• 2013 中華民國資訊學會最佳碩博士論文獎 (學生王耀德)
• 2013 IEEE Tainan 最佳碩士論文 (李怡樺)
• 2013 台灣電機電子工程學會(TIEEE)最佳博碩士論文 優等獎 (李怡樺)
• 中華民國資訊學會碩士最佳論文
• 2012 大學校院積體電路電腦輔助設計(CAD)軟體製作競賽 平台開發組 特優

主辦及參與國際會議

• Asia and South Pacific Design Automation Conference, (2022)
  
• Asia and South Pacific Design Automation Conference, (2021)
• Design Automation Conference(2018)
  
• Design Automation Conference(2015)
• Workshop on Compiler Techniques and System Software for High-Performance and Embedded Computer(2015)
• International Conference on Computer Aided Design(2014)
• International Conference on Computer Aided Design(2013)
• Asian Symposium on Quality Electronic Design(2012)
• International Symposium on Low Power Electronics and Design(2011)
• Asian and South Pacific Design Automation Conference, 2010(2010)
• Design Automation Conference, 2008(2008)